EP9132 Просмотр технического описания (PDF) - Unspecified
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EP9132 Datasheet PDF : 26 Pages
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Section 3 Detail Functional Descriptions
User Guide — EP9132_UG V0.1
3.1 General
The chip provides an IIC (SCL3/SDA3) serial bus interface to communicate with the host. The IIC address
for this slave IIC interface is "0111_A2_A1_A1_x" (where x=1 for read and x=0 for write). A2, A1 and A0
are programmable by pins
3.2 IIC Interface
The IIC bus interface uses a Serial Data line (SDA at pin SDA3) and a Serial Clock Line (SCL at pin SCL3)
for data transfer. The chip acts as a slave for receiving and transmitting data over the serial interface. All
devices connected to the IIC bus must have open drain or open collector outputs. Logic AND function is
exercised on both lines with external pull-up resistors, the value of these resistors is system dependent.
When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external
pull-up resistors.
Data received or transmitted on the SDA line must be stable at the positive edge of SCL. If the SDA changes
state while SCL is HIGH, the IIC interface interprets that action as a START or STOP sequence. Data on
SDA must change only when SCL is LOW.
The standard IIC traffic protocol is illustrated in the following Figure:
Figure 3-1 IIC Bus Transmission Protocol
MSB
LSB
SCL
1 2 34 5 6 78 9
MSB
LSB
1 2 34 5 6 78 9
SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX D7 D6 D5 D4 D3 D2 D1 D0
Start
Signal
Calling Address
Read/ Ack
Write Bit
MSB
LSB
SCL
1 2 34 5 67 89
Data Byte
No Stop
Ack Signal
Bit
MSB
LSB
1 234 5 678 9
SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
Calling Address
Read/ Ack Repeated
Write Bit
Start
Signal
New Calling Address
Read/ No Stop
Write
Ack Signal
Bit
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