BLOCK DIAGRAM
INIT
A10
A9
A8
A7
A6
A5
ROW
DECODER
1 OF 64
64 X 256
PROGRAMMABLE
ARRAY
8 X 1 OF 32
MULTIPLEXER
A4
A3
COLUMN
A2
DECODER
A1
1 OF 32
A0
OE/OES
CP
DQ
C
PROGRAMMABLE
MULTIPLEXER
8-BIT
EDGE-
TRIGGERED
REGISTER
CP
WS57C45
O7
O6
O5
O4
O3
O2
O1
O0
TEST LOAD (High Impedance Test Systems)
2.01 V
98 Ω
D.U.T.
30 pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
A.C. TESTING INPUT/OUTPUT WAVEFORM
3.0
1.5
TEST
1.5
POINTS
0.0
A.C. testing inputs are driven at 3.0 V for a logic “1” and 0.0 V
for a logic “0.” Timing measurements are made at 1.5 V for
input and output transitions in both directions.
AC READ TIMING DIAGRAM
A0-A10
OES
CP
O0-O7
tHA
tSA tHA
tSOES tHOES
tSOES tHOES
tSOES
tPWC
tHOES
tPWC
tPWC
tPWC
tPWC
tPWC
tCO
tHZC
tLZC
tCO
OE
tDI tRI
tHZOE
tLZOE
INIT
tPWI
2-23