T4312816A Просмотр технического описания (PDF) - Taiwan Memory Technology
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T4312816A Datasheet PDF : 29 Pages
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tm TE
CH
Preliminary T4312816A
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLOCK
SS
*N o te2
SS
SS
*N o te4
CKE
*N o te1
*N o te3
SS
tR C m in
SS
*N o te6
tSS
SS
CS
SS
SS
*N o te5
SS
RAS
SS
SS
CAS
SS
SS
SS
*N o te7
SS
SS
SS
SS
ADDR
SS
SS
SS
SS
BA
SS
SS
SS
SS
A 1 0 /A P
SS
SS
DQ
H i-z
SS
H i-z
SS
SS
SS
WE
SS
SS
SS
SS
DQM
SS
SS
S elf R efresh E n try
S elf R efresh E x it
A uto R efresh
:D o n 't c a re
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs inculding the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays ‘Low’.
Cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.
TM Technology Inc. reserves the right
P.27
to change products or specifications without notice.
Publication Date: APR. 2003
Revision: 0.B
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