ADSP-21060(RevH) Просмотр технического описания (PDF) - Analog Devices

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производитель

ADSP-21060
(Rev.:RevH)

SHARC Processor

Analog Devices 

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Table 27. Link Ports—Transmit

5V

3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

tSLACH

LACK Setup Before LCLK High

19

19

ns

tHLACH

LACK Hold After LCLK High

–6.75

–6.5

ns

Switching Characteristics

tDLCLK

tDLDCH

tHLDCH

tLCLKTWL

tLCLKTWH

tDLACLK

Data Delay After CLKIN

Data Delay After LCLK High1

Data Hold After LCLK High2

LCLK Width Low3

LCLK Width High4

LCLK Low Delay After LACK High

–2.0

(tCK/4) – 1

(tCK/4) – 1.25

(tCK/4) + 9

8

2.25

(tCK/4) + 1.25

(tCK/4) + 1

(3  tCK/4) + 16.5

–2

(tCK/4) – 0.75

(tCK/4) – 1.5

(tCK/4) + 9

8

ns

2.25

ns

ns

(tCK/4) + 1.5

ns

(tCK/4) + 1

ns

(3  tCK/4) + 16.5 ns

1 For ADSP-21060/ADSP-21060C, specification is 2.5 ns max.

2 For ADSP-21062L, specification is –2.25 ns min.

3 For ADSP-21060, specification is (tCK/4) – 1 ns min, (tCK/4) + 1 ns max; for ADSP-21060C/ADSP-21062L, specification is (tCK/4) – 1 ns min, (tCK/4) + 1.5 ns max.

4 For ADSP-21060, specification is (tCK/4) – 1 ns min, (tCK/4) + 1 ns max; for ADSP-21060C, specification is (tCK/4) – 1.5 ns min, (tCK/4) + 1 ns max.

Rev. H | Page 41 of 64 | March 2013

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