ADSP-21060(RevH) Просмотр технического описания (PDF) - Analog Devices

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ADSP-21060
(Rev.:RevH)

SHARC Processor

Analog Devices 

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

EXTERNAL POWER DISSIPATION (3.3 V)

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved.

Internal power dissipation is calculated in the following way:

PINT = IDDIN  VDD

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• the number of output pins that switch during each cycle

(O)

• the maximum frequency at which they can switch (f)

• their load capacitance (C)

• their voltage swing (VDD)

and is calculated by:

PEXT = O  C  VDD2  f

The load capacitance should include the processor’s package

capacitance (CIN). The switching frequency includes driving

the load high and then back low. Address and data pins can

drive high and low at a maximum rate of 1/(2tCK). The write

strobe can switch every cycle at a frequency of 1/tCK. Select pins

switch at 1/(2tCK), but selects can switch on each cycle.

Example: Estimate PEXT with the following assumptions:

• A system with one bank of external data memory RAM

(32-bit)

• Four 128K  8 RAM chips are used, each with a load of

10 pF

• External data memory writes occur every other cycle, a rate

of 1/(4tCK), with 50% of the pins switching

• The instruction cycle rate is 40 MHz (tCK = 25 ns)

The PEXT equation is calculated for each class of pins that can

drive:

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

PTOTAL = PEXT + (IDDIN2  3.3 V)

Note that the conditions causing a worst-case PEXT are different

from those causing a worst-case PINT. Maximum PINT cannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

Table 6. External Power Calculations (3.3 V Devices)

Pin Type

Address

MS0

WR

Data

ADDRCLK

No. of Pins

15

1

1

32

1

% Switching

50

0

–

50

–

C

 44.7 pF

 44.7 pF

 44.7 pF

 14.7 pF

 4.7 pF

f

 10 MHz

 10 MHz

 20 MHz

 10 MHz

 20 MHz

 VDD2

 10.9 V

 10.9 V

 10.9 V

 10.9 V

 10.9 V

= PEXT

= 0.037 W

= 0.000 W

= 0.010 W

= 0.026 W

= 0.001 W

PEXT = 0.074 W

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed Table 7 may cause permanent

damage to the device. These are stress ratings only; functional

operation of the device at these or any other conditions greater

than those indicated in the operational sections of this specifica-

tion is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Table 7. Absolute Maximum Ratings

Parameter

Supply Voltage (VDD)

Input Voltage

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Lead Temperature (5 seconds)

Junction Temperature Under Bias

ADSP-21060/ADSP-21060C

ADSP-21062

5V

–0.3 V to +7.0 V

–0.5 V to VDD + 0.5 V

–0.5 V to VDD + 0.5 V

200 pF

–65C to +150C

280C

130C

ADSP-21060L/ADSP-21060LC

ADSP-21062L

3.3 V

–0.3 V to +4.6 V

–0.5 V to VDD +0.5 V

–0.5 V to VDD + 0.5 V

200 pF

–65C to +150C

280C

130C

Rev. H | Page 20 of 64 | March 2013

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