SPT5420SIM(2001) Просмотр технического описания (PDF) - Signal Processing Technologies

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Компоненты Описание

производитель

SPT5420SIM
(Rev.:2001)

13-BIT, OCTAL D/A CONVERTER

Signal Processing Technologies 

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Supply Voltages

VCC ........................................................................ +6 V

VDD ...................................................................... +15 V

VSS ...................................................................... –15 V

Temperature

Operating Temperature .......................... –40 to +85 °C

Storage ................................................ –65 to +150 °C

Input Voltages

VREFT .................................... VSS –0.3 V to VDD +0.3 V

VREFB ................................... VDD +0.3 V to VSS –0.3 V

Digital inputs ....................................–0.3 V to VCC +0.3 V

Note: 1. Operation at any Absolute Maximum Rating is not implied. See

Electrical Specifications for proper nominal applied conditions

in typical applications.

ELECTRICAL SPECIFICATIONS

TA = TMIN to TMAX, VCC = +5.0 V, VDD = +11.5 V, VSS = –8.0 V, VREFT=3.5 V, VREFB = –1.5 V, RL = +10 kΩ, CL = 50 pF, unless otherwise specified.

PARAMETERS

TEST

CONDITIONS

TEST

LEVEL

SPT5420

MIN

TYP

MAX

UNITS

Accuracy

Resolution

Integral Linearity Error (ILE)

Differential Linearity Error (DLE)

Zero-Scale Error

Full Scale Error

Gain Error

VI

13

VI

–2.0

VI

–1.0

VI

–25

VI

–25

VI

–25

±0.5

±0.3

Bits

+2.0

LSB

+1.0

LSB

+25

mV

+25

mV

+25

mV

Reference Inputs

Input Current

VREFT1

VREFB2

RGND Inputs

DC Input Impedance

Input Range

IV

VI

0

VI

–5.0

V

IV

–2.0

+3.5

–1.5

60

±100

nA

+5.0

V

0

V

kΩ

2.0

V

Output Characteristics

Output Swing3,4

Short Circuit Current

Resistive Load

DC Output Impedance

Digital Inputs

Logic 1 Voltage

Logic 0 Voltage

Maximum Input Current

Input Capacitance

VI

+7/–3

IV

VI

5

IV

VI

2.4

VI

VI

–10

V

10

V

15

mA

kΩ

1.0

Ω

V

0.8

V

10

µA/pin

pF

Notes:

1. VREFT < 8 V + (VSS x 0.5); e.g., if VSS = –8 V, then VREFT < 4 V

2. VREFB > (VDD x 0.5) – 9.5 V; e.g., if VDD = 11 V, then VREFB > –4 V

3. VSS + 2.5 V ≤ VOUT ≤ VSS + 16.0 V for 18.5 V ≤ VDD – VSS ≤ 20.0 V

VSS + 2.5 V ≤ VOUT ≤ VDD – 2.5 V for VDD – VSS ≤ 18.5 V

INPUT CODE

4. VOUT = 2 X (VREFB +[VREFT – VREFB] X 8192 ) – VRGND

SPT

2

SPT5420

6/26/01

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