LT1055ACH-PBF(Rev_D) Просмотр технического описания (PDF) - Linear Technology
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LT1055ACH-PBF Datasheet PDF : 20 Pages
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TYPICAL PERFORMANCE CHARACTERISTICS
LT1055/LT1056
Supply Current vs Supply Voltage
8
6
TA = – 55°C
LT1056
4 25°C
TA = 125°C
LT1055 TA = – 55°C
25°C
2
TA = 125°C
0
0
5
10
15
20
SUPPLY VOLTAGE (V)
LT1055/56 G25
Output Swing vs Load Resistance
15
12 TA = – 55°C
9
6
TA = –25°C
3 TA = –125°C
0
VS = ±15V
–3
–6
TA = –25°C
–9
–12 TA = – 55°C
TA = –125°C
–15
0.1
0.3
1
3
10
LOAD RESISTANCE (kΩ)
LT1055/56 G26
Short-Circuit Current vs Time
50
40
TA = – 55°C
TA = 25°C
30
TA = 125°C
20
10
0 VS = ±15V
–10
–20
–30
SINKING
TA = 125°C
TA = 25°C
–40
–50
0
TA = – 55°C
1
2
3
TIME FROM OUTPUT SHORT TO GROUND
(MINUTES)
LT1055/56 G27
APPLICATIONS INFORMATION
The LT1055/LT1056 may be inserted directly into LF155A/
LT355A, LF156A/LT356A, OP-15 and OP-16 sockets.
Offset nulling will be compatible with these devices with
the wiper of the potentiometer tied to the positive supply.
Offset Nulling
V+
1 RP
2–
57
LT1055
LT1056
3+
4
V–
6 OUT
LT1055/56 AI1
No appreciable change in offset voltage drift with tem-
perature will occur when the device is nulled with a
potentiometer, RP, ranging from 10k to 200k.
The LT1055/LT1056 can also be used in LF351, LF411,
AD547, AD611, OPA-111, and TL081 sockets, provided
that the nulling cicuitry is removed. Because of the LT1055/
LT1056’s low offset voltage, nulling will not be necessary
in most applications.
example, leakage currents in circuitry external to the op
amp can significantly degrade performance. High quality
insulation should be used (e.g. Teflon, Kel-F); cleaning of
all insulating surfaces to remove fluxes and other resi-
dues will probably be required. Surface coating may be
necessary to provide a moisture barrier in high humidity
environments.
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs: in inverting configurations the guard ring
should be tied to ground, in noninverting connnections
to the inverting input at pin 2. Guarding both sides of the
N/C
OFFSET
V+
TRIM
OUTPUT
OFFSET
TRIM
7
8
1
6
5
4
2
3
Achieving Picoampere/Microvolt Performance
In order to realize the picoampere-microvolt level accuracy
of the LT1055/LT1056 proper care must be exercised. For
V–
GUARD
For more information www.linear.com/LT1055
LT1055/56 AI2
10556fd
9
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