SAA4978 Просмотр технического описания (PDF) - Philips Electronics

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производитель

SAA4978

Picture Improved Combined Network (PICNIC)

Philips Electronics 

Philips Semiconductors

Picture Improved Combined Network

(PICNIC)

Product specification

SAA4978H

handbook, halfpage

1

40

120

SAA4978H

81

MHB174

Fig.3 Pin configuration.

7 FUNCTIONAL DESCRIPTION

The SAA4978H consists of the following main functional

blocks:

• Analog preprocessing and analog-to-digital conversion

• Digital processing at 1fH level

• Digital processing at 2fH level

• Digital-to-analog conversion

• Line-locked clock generation

• Crystal oscillator

• Control interfacing I2C-bus and SNERT

• Register I/O

• Programmable Signal Positioner (PSP)

• 80C51 microcontroller core

• Board level testability provisions.

7.1 Analog input blocks

7.1.1

GAIN ELEMENTS FOR AUTOMATIC GAIN CONTROL

(9 dB RANGE)

A variable amplifier is used to map the possible YUV input

range to the analog-to-digital converter range e.g. as

defined for SCART signals.

According to this specification, a lift of 6 dB up to a drop of

3 dB may be necessary with respect to the nominal values.

The gain setting within the required minimum 9 dB range

is performed digitally via the internal microcontroller.

For this purpose a gain setting digital-to-analog converter

is incorporated. The smallest step in the gain setting

should be hardly visible on the picture, this can be met with

smaller steps of 0.4%/step.

Luminance and chrominance gain settings can be

separately controlled. The reason for this split is that

U and V may have already been gain adjusted by an

Automatic Chrominance Control (ACC), whereas

luminance is to be adjusted by the SAA4978H AGC.

However, for RGB originated sources, Y, U and V should

be adjusted with the same AGC gain.

7.1.2

CLAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 32

AND UV TO 0 (TWOS COMPLEMENT)

A clamp circuit is applied to each input channel, to map the

colourless black level in each video line (on the sync back

porch) to level 32 at 9 bits for Y and to the centre level of

the converters for U and V. During the clamp period, an

internally generated clamp pulse is used to switch-on the

clamp action.

1999 May 03

10

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