FW801 Просмотр технического описания (PDF) - Agere -> LSI Corporation
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FW801 Datasheet PDF : 22 Pages
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FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Signal Information
Data Sheet, Rev. 1
June 2001
CTL0 1
CTL1 2
D0 3
D1 4
VDD 5
D2 6
D3 7
D4 8
D5 9
D6 10
D7 11
VSS 12
PIN #1 IDENTIFIER
AGERE FW801
36 VSSA
35 VSSA
34 VDDA
33 VDDA
32 TPBIAS0
31 TPA0+
30 TPA0–
29 TPB0+
28 TPB0–
27 VSSA
26 VSSA
25 VDDA
Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Figure 2. Pin Assignments
5-7302.b (F)
Table 1. Signal Descriptions
Pin
Signal* Type
Name/Description
17
C/LKON I/O Bus Manager Capable Input and Link-On Output. On hardware reset, this pin is
used to set the default value of the contender status indicated during self-ID. The
bit value programming is done by tying the signal through a 10 kΩ resistor to VDD
(high, bus manager capable) or to GND (low, not bus manager capable). Using
either the pull-up or pull-down resistor allows the link-on output to override the input
value when necessary.
After hardware reset, this pin is set as an output, C/LKON indicates the reception of
a link-on message by asserting a 6.114 MHz signal.
13
CNA
O Cable-Not-Active Output. CNA is asserted high when none of the PHY ports are
receiving an incoming bias voltage. This circuit remains active during the power-
down mode.
20
CPS
I Cable Power Status. CPS is normally connected to the cable power through a
400 kΩ resistor. This circuit drives an internal comparator that detects the presence
of cable power. This information is maintained in one internal register and is avail-
able to the LLC by way of a register read (see IEEE P1394a Draft 2.0 Standard for
a High Performance Serial Bus (Supplement)).
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
6
Agere Systems Inc.
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