MT90500AL Просмотр технического описания (PDF) - Mitel Networks
Номер в каталоге
Компоненты Описание
производитель
MT90500AL Datasheet PDF : 159 Pages
| |||
MT90500
VC Look-up
Tables
TX / RX Control
Structures and
Circular Buffers
External
Synchronous
SRAM
MT90500
To/From Main
External UTOPIA
PHY
Interface
From
External
SAR
Secondary
UTOPIA
Interface
TX UTOPIA
MUX
RX
UTOPIA
BLOCK
UTOPIA Module
External Memory
Controller
TDM Module
TX
AAL1
SAR
RX
AAL1
SAR
Internal
TDM
Frame
Buffer
TDM Bus
Interface
Logic
TDM Clock
Logic
Clock
Recovery
Registers
TDM Bus
16 lines
2048 x 64kbps
(max.)
Local TDM Bus
32 x 64 kbps in /
32 x 64 kbps out
Clock
Signals
Boundary-
Scan Logic
Microprocessor
Interface Logic
JTAG Interface
16-bit Microprocessor Inter-
face
Figure 1 - MT90500 Block Diagram
1.2 Reference Documents
MT90500 Programmer’s Manual.
MSAN-171 - TDM Clock Recovery from CBR-over-ATM Links Using the MT90500.
ITU-T Rec. I.363.1, “B-ISDN ATM Adaptation Layer Specification: Type 1 AAL,” 08/1996.
ANSI T1.630, “Broadband ISDN - ATM Adaptation Layer for Constant Bit Rate Services Functionality and
Specification,” 1993.
AF-PHY-0017, “UTOPIA, An ATM-PHY Interface Specification: Level 1, Version 2.01,” March 21, 1994.
AF-VTOA-0078.000, “Circuit Emulation Service Interoperability Specification, Version 2.0,” Jan. 1997.
AF-VTOA-0083.000, “Voice and Telephony Over ATM to the Desktop Specification, Version 2.0,” May 1997.
M. Noorchasm et al., “Buffer Design for Constant Bit Rate Services in Presence of Cell Delay Variation,” ATM
Forum Contribution 95-1454.
Paul E. Fleischer and Chi-Leung Lau, “Synchronous Residual Time Stamp for Timing Recovery in a Broadband
Network,” United States Patent 5,260,978, Nov. 1993.
IEEE Std. 1149.1a-1993, “IEEE Standard Test Access Port and Boundary Scan Architecture.”
12
Share Link: 