GENERAL DESCRIPTION
The UT52L1616 is a high-speed CMOS dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual memory array (512K x 16) with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the two internal banks is organized with 2,048 rows and with either 256 columns by 16 bits.

FEATURES
● PC100 compliant functionality and performance.
● JEDEC standard 3.3 V ± 10% power supply.
● LVTTL compatible inputs and outputs.
● All inputs are sampled on positive edge of system clock.
● Dual Banks for hidden row access/precharge.
● Internal pipeline operation, column addresses can be changed every cycle.
● DQM for masking.
● MRS cycle with address key programmability for:
   - CAS latency ( 2 , 3 )
   - Burst Length ( 1 , 2 , 4 , 8 or full page)
   - Burst Type ( Sequential & Interleave )
● Auto Precharge and Auto Refresh modes.
● Self Refresh Mode.
● 64ms , 4096 cycle refresh ( 15.6 us/row )
● 50–pin 400 mil plastic TSOP (type II) package.