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SMJ4C1024 Datasheet - Austin Semiconductor

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SMJ4C1024

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MFG CO.
Austin-Semiconductor
Austin Semiconductor Austin-Semiconductor

description
The SMJ4C1024 is a 1048576-bit DRAM organized as 1048576 words of one bit each. It employs technology for high performance, reliability, and low power at a low cost.
This device features maximum RAS access times of 80 ns, 100 ns, 120 ns, and 150 ns. Maximum power dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices.
IDD peaks are typIcally 140 mA and a –1 V input voltage undershoot can be tolerated, minimizing system noise.
All inputs and outputs, including clocks, are compatible with series 54 TTL. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ4C1024 is offered in an 18-pin ceramic dual-in-line package (JD suffix), a 20/26-terminal leadless ceramic carrier package (FQ/HL suffixes), a 20/26-pin J-leaded carrier package (HJ suffix), a 20-pin flatpack (HK suffix), and a 20-pin ceramic zig-zag in-line package (SV suffix). They are characterized for operation from – 55°C to 125°C.

• Organization . . . 1048576 × 1-Bit
• Processed to MIL-STD-883, Class B
• Single 5-V Supply (10% Tolerance)
• Performance Ranges:
               ACCESS ACCESS ACCESS READ
               TIME   TIME  TIME  OR
               ta(R) ta(C) ta(CA) WRITE
              (tRAC) (tCAC) (tAA) CYCLE
              (MAX) (MAX) (MAX) (MIN)
   ’4C1024-80 80 ns 20 ns 40 ns 150 ns
   ’4C1024-10 100 ns 25 ns 45 ns 190 ns
   ’4C1024-12 120 ns 30 ns 55 ns 220 ns
   ’4C1024-15 150 ns 40 ns 70 ns 260 ns
 Enhanced Page-Mode Operation for Faster Memory Access
   – Higher Data Bandwidth Than Conventional Page Mode Parts
   – Random Single-Bit Access Within a Row With a Column Address
• One of TI’s CMOS Megabit Dynamic
   Random-Access Memory (DRAM) Family
   Including SMJ44C256 — 256K × 4
   Enhanced Page Mode
• CAS-Before-RAS (CBR) Refresh
• Long Refresh Period 512-Cycle Refresh in 8 ms (Max)
• 3-State Unlatched Output
• Low Power Dissipation
• All Inputs/Outputs and Clocks Are TTL-Compatible
• Packaging Offered:
   – 20/26-Pin J-Leaded Ceramic Surface Mount Package (HJ Suffix)
   – 18-Pin 300-Mil Ceramic Dual-In-Line Package (JD Suffix)
   – 20-Pin Ceramic Flatpack (HK Suffix)
   – 20/26-Terminal Leadless Ceramic Surface Mount Package (FQ/HL Suffixes)
   – 20-Pin Ceramic Zig-Zag In-Line Package (SV Suffix)
• Operating Temperature Range – 55°C to 125°C

 

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