Functional Description
General 
The SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive recursive filter to achieve a reduction of noise for video signals. To get a closed loop one of the two output ports of the triple port memory is connected internally to the noise reduction filter. External access to this port is not possible. The characteristic of the noise reduction filter is adjustable via three pins (CLASS2, CLASS1, CLASS0).

FEATUREs
● Stores a complete video field (4:1:1)
● On chip adaptive recursive noise reduction filter (4:1:1)
● 4 noise reduction classes selectable
● Special noise reduction mode for 4:2:2 applications
● 212 × 64 × 16 × 12-bit organization
● Triple port architecture
● One 16 × 12-bit input shift register
● Two 16 × 12-bit output shift registers
● Shift registers independently and simultaneously
   accessible (one output shift register is used internally for
   noise reduction filtering)
● Continuous data flow even at maximum speed
● 40-MHz shift rate - 0.96-Gbit/s total data rate
● All inputs and outputs TTL-compatible
● Tristate outputs
● Random access of groups of 16 × 12 bits for a wide range
   of applications
● Refresh-free operation possible
● 5 V ± 10 % power supply
● 0 … 70 °C operating temperature range
● Low power dissipation: 700 mW active, 28 mW standby
● Suitable for all common TV standards
● Allows flicker and noise reduction simultaneously
   with only one field memory
● Applications: TV, VCR, image processing,
   video printers, data compressors, delay lines,
   time base correctors, HDTV