The Dynex Semiconductor MA31750 is a single-chip microprocessor that implements the full MIL-STD-1750A instruction set architecture, or Option 2 of Draft MIL-STD-1750B. The processor executes all mandatory instructions and many optional features are also included. Interrupts, fault handling, memory expansion, Console, timers A and B, and their related optional instructions are also supported in full accordance with MIL-STD-1750.

ARCHITECTURE
The Dynex Semiconducor MA31750 Microprocessor is a high performance implementation of the MIL-STD-1750A (Notice 1) Instruction Set Architecture. Figure 1 depicts the architectural details of the chip. Two key features of this architecture which contribute to the overall high performance of the MA31750 are a 32-bit shift network and a 24-bit parallel multiplier. These sub-systems allow the MA31750 to perform multi-bit shifts, multiplications,divisions and normalisations in a fraction of the clock cycles required on machines not having such resources. This is especially true of floating-point operations, in which the MA31750 excels. Such operations constitute a large proportion of the Digital Avionics Instruction Set (DAIS) mix and generally a high percentage of many signal processing algorithms, therefore having a significant impact on system performance.

KEY FEATUREs include:
1) A three-bus (R, S, and Y) datapath consisting of an arithmetic/logic unit (ALU), three-port register file, shift network, parallel multiplier and flags block;
2) Four instruction fetch registers C0,C1, IA, and IB;
3) Two operand transfer registers DI, and DO;
4) Two address registers IC and A;
5) A state sequencer;
6) Micro-instruction decode logic.