datasheetbank_Logo
전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크
HOME  >>>  LSI Corporation   >>> ZSP200 PDF

ZSP200 데이터시트 - LSI Corporation

ZSP200 image

부품명
ZSP200

Other PDF
  no available.

PDF
DOWNLOAD     

page
2 Pages

File Size
56.6 kB

제조사
LSI
LSI Corporation  

OVERVIEW
The ZSP540 processor core is a high-performance/power-efficient QuadMAC/Six-ALU implementation of the ZSP®G2 architecture. The ZSP540 utilizes a 16-bit architecture with extensive 32-bit capabilities and sets an unmatched balance of performance/power/size and memory utilization efficiency. The Z.Turbo feature provides the SOC designer with the option to extend the ZSP540 Instruction Set and the ability to add application-specific acceleration logic.

CORE FEATURES
• Quad-MAC/Six-ALU DSP core
• 4+1 instructions per cycle
• Up to 350MHz, 8-stage pipeline design
• Up to 1750 million instructions/sec
• Dual 64-bit wide Load/Store data ports
• Z.Turbo coprocessor extensions capable
• 24-bit address space
• HW managed instructions scheduling
• HW/SW controlled power management
• Real-time trace and profiling capability
• Full AMBA/AHB support (optional)
• JTAG debug interface
• Static, single phase clocked design
• Compatible with all other ZSP cores

ARCHITECTURE FEATURES
• Embedded control processing efficiency
• 32-bit addressing capabilities
• 16 and 32-bit standard instruction set
• Extensive 32-bit and 40-bit support
• Easy to program instruction set
• Load/store register based instructions
• Outstanding code density
• User extensible instruction set


APPLICATION BENEFITS
•High-performance DSP capabilities
•Excellent power/cost/speed balance
•Excellent multimedia audio/video processing
•Power efficient baseband processing performance
•DSP and system control functions handling capabilities
CORE FEATURES
• Quad-MAC/Six-ALU DSP core
• 4+1 instructions per cycle
• Up to 350MHz, 8-stage pipeline design
• Up to 1750 million instructions/sec
• Dual 64-bit wide Load/Store data ports
• Z.Turbo coprocessor extensions capable
• 24-bit address space
• HW managed instructions scheduling
• HW/SW controlled power management
• Real-time trace and profiling capability
• Full AMBA/AHB support (optional)
• JTAG debug interface
• Static, single phase clocked design
• Compatible with all other ZSP cores
ARCHITECTURE FEATURES
• Embedded control processing efficiency
• 32-bit addressing capabilities
• 16 and 32-bit standard instruction set
• Extensive 32-bit and 40-bit support

Page Link's: 1  2 

부품명
상세내역
보기
제조사
Highly Efficient 3A Synchronous Buck Regulator
PDF
Intersil
16-bit Fixed Point DSP Core
PDF
Samsung
Quad-SHARC DSP Multiprocessor
PDF
Analog Devices
Quad Core Driver Transistor
PDF
ON Semiconductor
Quad Core Drier Transistor
PDF
Motorola => Freescale
MTK6589 - Quad Core 1.2Ghz
PDF
Samsung
Quad-SHARC® DSP Multiprocessor Family ( Rev : RevB )
PDF
Analog Devices
Quad-SHARC® DSP Multiprocessor Family
PDF
Analog Devices
Quad-SHARC® DSP Multiprocessor Family
PDF
Analog Devices
16-Bit Fixed Point Digital Signal Processor (DSP) Core
PDF
STMicroelectronics

Share Link: GO URL

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]