Dual 4−Stage Binary Ripple Counter with ÷2 and ÷5 Sections
High–Performance Silicon–Gate CMOS

TheMC54/74HC390 is identical in pinout tothe LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4–bit counters, each composed ofa divide–by–two and a divide–by–five section. The divide–by–two and divide–by–five counters have separate clock inputs, and can be cascaded to
implement various combinations of ÷2 and/or ÷5 up to a ÷100 counter.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates