
Fujitsu
■ DESCRIPTION
MB86941 and MB86942 are dedicated peripheral LSIs for SPARClite*.
The MB86941 and MB86942 are designed to enable compact configuration of high-performance systems with SPARClite architecture, and provide the following features.
■ FEATURES
Direct connection to SPARClite
Register read/write in 2 clock cycles up to 30MHz.
Register read/write in 3 clock cycles at 40MHz (MB86941) or 50MHz (MB86942).
Built-In On-Chip Modules:
• Interrupt controller
Interrupt input: 15 channels
Each interrupt input has independent masking and trigger mode settings
• 16-bit timer: 4 channels
Two of the four channels have prescalers
Each channel has five independent mode operations
MODE0 : Periodical-interrupt
MODE1 : Timeout-interrupt
MODE2 : Square wave generator
MODE3: Programmable one shot (software trigger)
MODE4: Programmable one shot (external trigger)
• SDTR (Serial data transmitter receiver): 2 channels MB89251A type
• Timing control, CS expansion
Generates read, write and data strobe signals according to the requirements of external devices.
• SIO (Synchronous serial input/output)
Simple synchronous type serial input/output
• I/O port, 16-bit
Individual direction control by bit
5V single power supply (MB86941), 3.3V single power supply (MB86942) Upward pin compatibility with MB86940C