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IDT82V2084
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IDT82V2084 데이터시트 - Renesas Electronics
Renesas Electronics
DESCRIPTION:
The IDT82V2084 can be configured as a quad T1, quad E1 or quad J1 Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to remove the distortion introduced by the cable attenuation. The IDT82V2084 also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and detects and reports the LOS conditions. In transmit path, there is an AMI/ B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter Attenuator for each channel, which can be placed in either the receive path or the transmit path. The Jitter Attenuator can also be disabled. The IDT82V2084 supports both Single Rail and Dual Rail system interfaces and both serial and parallel control interfaces. To facilitate the network maintenance, a PRBS/QRSS generation/detection circuit is integrated in each channel, and different types of loopbacks can be set on a per channel basis. Four different kinds of line terminating impedance, 75Ω, 100 Ω, 110 Ω and 120 Ω are selectable on a per channel basis. The chip also provides driver short-circuit protection and supports JTAG boundary scanning.
The IDT82V2084 can be used in SDH/SONET, LAN, WAN, Routers, Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, CSU/DSU equipment, etc.
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