1.SUMMARY DESCRIPTION
Hynix NAND HY27UF(08/16)4G2B Series have 512Mx8bit with spare 16Mx8 bit capacity. The device is offered in 3.3 Vcc Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the mostcost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 4096 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 1.5ms on a 128K-byte block.
Data in the page can be read out at 25ns cycle time per byte(x8). The I/O pins serve as the ports for address and data input/output as wellas command input.

FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
MULTIPLANE ARCHITECTURE
- Array is split into two independent planes. Parallel Operations on both planes are available, halving Program and erase time.
NAND INTERFACE
- x8/x16 bus width.
- Address/ Data Multiplexing
- Pinout compatiblity for all densities
SUPPLY VOLTAGE
- 3.3V device : Vcc = 2.7 V ~3.6 V
MEMORY CELL ARRAY
- x8 : (2K + 64) bytes x 64 pages x 4096 blocks
- x16 : (1K + 32) words x 64 pages x 4096 blocks
PAGE SIZE
- (2K + 64 spare) Bytes
- (1K + 32 spare) Words
BLOCK SIZE
- (128K + 4Kspare) Bytes
- (64K + 2Kspare) Words
PAGE READ / PROGRAM
- Random access : 25us (max.)
- Sequential access : 25ns (min.)
- Page program time : 200us (typ.)
- Multi-page program time (2 pages) : 200us (Typ)
COPY BACK PROGRAM
- Automatic block download without latency time
FAST BLOCK ERASE
- Block erase time: 1.5ms (Typ)
- Multi-block erase time (2 blocks) : 1.5ms (Typ) STATUS REGISTER
- Normal Status Register (Read/Program/Erase)
- Extended Status Register (EDC)
ELECTRONIC SIGNATURE
- 1st cycle : Manufacturer Code
- 2nd cycle : Device Code
- 3rd cycle : Internal chip number, Cell Type, Number of Simultaneously Programmed Pages.
- 4th cycle : Page size, Block size, Organization, Spare size
- 5th cycle : Multiplane information
CHIP ENABLE DON’T CARE
- Simple interface with microcontroller HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions. DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/528byte ECC)
- 10 years Data Retention
PACKAGE
- HY27UF(08/16)4G2B-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UF(08/16)4G2B-T (Lead)
- HY27UF(08/16)4G2B-TP (Lead Free)