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CP716V
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Central Semiconductor
CP716V(2005) 데이터시트 - Central Semiconductor
Central Semiconductor
PROCESS DETAILS
Process EPITAXIAL PLANAR
Die Size 20 x 20 MILS
Die Thickness 7.1 MILS
Base Bonding Pad Area 4.0 x 4.0 MILS
Emitter Bonding Pad Area 4.7 x 4.7 MILS
Top Side Metalization Al - 30,000Å
Back Side Metalization Au - 18,000Å
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제조사
Small Signal Transistors PNP - High Voltage Transistor Chip ( Rev : 2005 )
Central Semiconductor
Small Signal Transistor PNP - High Voltage Transistor Chip ( Rev : 2002 )
Central Semiconductor
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