• Organization: 262,144 words × 16 or 18 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4/5 ns
• Fast OE access time: 3.5/3.5/3.8/5.0 ns
• Fully synchronous register-to-register operation
• “Flow-through” mode
• Single-cycle deselect
- Double-cycle deselect also available (AS7C3256PFD16A/AS7C3256PFD18A)
• Pentium® compatible architecture and timing
• Synchronous and asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Automatic power down: 30 mW typical standby power
• NTD™ pipeline architecture available
(AS7C3256NTD16A/AS7C3256NTD18A)