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AS5SP128K36DQ 데이터시트 - Austin Semiconductor

AS5SP128K36DQ image

부품명
AS5SP128K36DQ

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page
10 Pages

File Size
277.3 kB

제조사
AUSTIN
Austin Semiconductor 

General Description
   ASI’s AS5SP128K36DQ is a 4.5Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 128K x 36. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock.


FEATUREs
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without Data
   Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE)
• Three Pin Burst Control (ADSP, ADSC, ADV)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
• Available in Industrial, Enhanced, and Mil-Temperature
   Operating Ranges


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