GENERAL DESCRIPTION
The ADSP-2192M is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications, and is ideally suited for PC peripherals.
The ADSP-2192M combines the ADSP-219x family base architecture (three computational units, two data address generators and a program sequencer) into a chip with two core processors (see the Functional Block Diagram on Page 1 and Figure 1).

ADSP-2192M DUAL CORE DSP FEATURES
   320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package
      with PCI, USB, Sub-ISA, and CardBus Interfaces
   3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface
      with Bus Mastering over Four DMA Channels with
      Scatter-Gather Support
   Integrated USB 1.1 Compliant Interface
   Sub-ISA Interface
   AC’97 Revision 2.1 Compliant Interface for External
      Audio, Modem, and Handset Codecs with DMA
      Capability
   Dual ADSP-219x Core Processors (P0 and P1) on Each
      ADSP-2192M DSP Chip
   132K Words of Memory Includes 4K x 16-Bit Shared
      Data Memory
   80K Words of On-Chip RAM on P0, Configured as
      64K Words On-Chip 16-Bit RAM for Data Memory and
      16K Words On-Chip 24-Bit RAM for Program Memory
   48K Words of On-Chip RAM on P1, Configured as
      32K Words On-Chip 16-Bit RAM for Data Memory and
      16K Words On-Chip 24-Bit RAM for Program Memory
   4K Words of Additional On-Chip RAM Shared by Both
      Cores, Configured as 4K Words On-Chip 16-Bit RAM
   Flexible Power Management with Selectable Power Down and Idle Modes
   Programmable PLL Supports Frequency Multiplication,
      Enabling Full Speed Operation from Low Speed
      Input Clocks
   2.5 V Internal Operation Supports 3.3 V/5.0 V
      Compliant I/O

DSP CORE FEATURES
   6.25 ns Instruction Cycle Time (Internal), for up to
      160 MIPS Sustained Performance
   ADSP-218x Family Code Compatible with the Same Easy
      to Use Algebraic Syntax
   Single-Cycle Instruction Execution
   Dual Purpose Program Memory for Both Instruction and
      Data Storage
   Fully Transparent Instruction Cache Allows Dual Operand
      Fetches in Every Instruction Cycle
   Unified Memory Space Permits Flexible Address
      Generation, Using Two Independent DAG Units
   Independent ALU, Multiplier/Accumulator, and Barrel
      Shifter Computational Units with Dual 40-Bit
      Accumulators
   Single-Cycle Context Switch between Two Sets of
      Computational and DAG Registers
   Parallel Execution of Computation and Memory
      Instructions
   Pipelined Architecture Supports Efficient Code Execution
      at Speeds up to 160 MIPS
   Register File Computations with All Nonconditional,
      Nonparallel Computational Instructions
   Powerful Program Sequencer Provides Zero-Overhead
      Looping and Conditional Instruction Execution
   Architectural Enhancements for Compiled C/C++ Code
      Efficiency
   Architecture Enhancements beyond ADSP-218x Family
      are Supported with Instruction Set Extensions for
      Added Registers, Ports, and Peripherals