General description
The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition.
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

FEATUREs
■ Balanced propagation delays
■ All inputs have Schmitt-trigger actions
■ Inputs accept voltages higher than VCC
■ Common 3-state output enable input
■ Input levels:
   ◆ For 74AHC374: CMOS level
   ◆ For 74AHCT374: TTL level
■ ESD protection:
   ◆ HBM EIA/JESD22-A114E exceeds 2000 V
   ◆ MM EIA/JESD22-A115-A exceeds 200 V
   ◆ CDM EIA/JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C