CLRC632 데이터 시트보기 (PDF) - NXP Semiconductors.

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CLRC632

Standard multi-protocol reader solution

NXP Semiconductors. 

NXP Semiconductors

CLRC632

Standard multi-protocol reader solution

22. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 4. Supported microprocessor and EPP interface

signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 5. Connection scheme for detecting the parallel

interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 6. SPI compatibility . . . . . . . . . . . . . . . . . . . . . . .10

Table 7. SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 8. SPI read address . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9. SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10. SPI write address . . . . . . . . . . . . . . . . . . . . . . 11

Table 11. EEPROM memory organization diagram . . . . .12

Table 12. Product information field . . . . . . . . . . . . . . . . .13

Table 13. Product type identification definition . . . . . . . .13

Table 14. Byte assignment for register initialization at

start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 15. Shipment content of StartUp configuration file .15

Table 16. Byte assignment for register initialization at

startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 17. Content of I-CODE1 startup configuration . . . .17

Table 18. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .19

Table 19. Associated FIFO buffer registers and flags . . .20

Table 20. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .21

Table 21. Interrupt control registers . . . . . . . . . . . . . . . .21

Table 22. Associated Interrupt request system registers

and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 23. TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . .26

Table 24. Associated timer unit registers and flags . . . . .27

Table 25. Signal on pins during Hard power-down . . . . .28

Table 26. Pin TX1 configurations . . . . . . . . . . . . . . . . . .31

Table 27. Pin TX2 configurations . . . . . . . . . . . . . . . . . .32

Table 28. TX1 and TX2 source resistance of n-channel

driver transistor against GsCfgCW or

GsCfgMod . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 29. Gain factors for the internal amplifier . . . . . . . .36

Table 30. DecoderSource[1:0] values . . . . . . . . . . . . . . .39

Table 31. ModulatorSource[1:0] values . . . . . . . . . . . . . .39

Table 32. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .39

Table 33. Register settings to enable use of the analog

circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 34. MIFARE higher baud rates . . . . . . . . . . . . . . .40

Table 35. ISO/IEC 14443 B registers and flags . . . . . . . .41

Table 36. Dedicated address bus: assembling the

register address . . . . . . . . . . . . . . . . . . . . . . . .43

Table 37. Multiplexed address bus: assembling the

register address . . . . . . . . . . . . . . . . . . . . . . . .44

Table 38. Behavior and designation of register bits . . . . .44

Table 39. CLRC632 register overview . . . . . . . . . . . . . . .45

Table 40. CLRC632 register flags overview . . . . . . . . . .47

Table 41. Page register (address: 00h, 08h, 10h, 18h,

20h, 28h, 30h, 38h) reset value: 1000 0000b,

80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .50

Table 42. Page register bit descriptions . . . . . . . . . . . . .50

Table 43. Command register (address: 01h) reset

value: x000 0000b, x0h bit allocation . . . . . . .50

Table 44. Command register bit descriptions . . . . . . . . . 50

Table 45. FIFOData register (address: 02h) reset value:

xxxx xxxxb, 05h bit allocation . . . . . . . . . . . . . 51

Table 46. FIFOData register bit descriptions . . . . . . . . . 51

Table 47. PrimaryStatus register (address: 03h) reset

value: 0000 0101b, 05h bit allocation . . . . . . . 51

Table 48. PrimaryStatus register bit descriptions . . . . . . 51

Table 49. FIFOLength register (address: 04h) reset

value: 0000 0000b, 00h bit allocation . . . . . . . 52

Table 50. FIFOLength bit descriptions . . . . . . . . . . . . . . 52

Table 51. SecondaryStatus register (address: 05h)

reset value: 01100 000b, 60h bit allocation . . . 53

Table 52. SecondaryStatus register bit descriptions . . . . 53

Table 53. InterruptEn register (address: 06h) reset

value: 0000 0000b, 00h bit allocation . . . . . . . 53

Table 54. InterruptEn register bit descriptions . . . . . . . . 53

Table 55. InterruptRq register (address: 07h) reset

value: 0000 0000b, 00h bit allocation . . . . . . . 54

Table 56. InterruptRq register bit descriptions . . . . . . . . 54

Table 57. Control register (address: 09h) reset value:

0000 0000b, 00h bit allocation . . . . . . . . . . . . 55

Table 58. Control register bit descriptions . . . . . . . . . . . 55

Table 59. ErrorFlag register (address: 0Ah) reset value:

0100 0000b, 40h bit allocation . . . . . . . . . . . . 55

Table 60. ErrorFlag register bit descriptions . . . . . . . . . . 55

Table 61. CollPos register (address: 0Bh) reset value:

0000 0000b, 00h bit allocation . . . . . . . . . . . . 56

Table 62. CollPos register bit descriptions . . . . . . . . . . . 56

Table 63. TimerValue register (address: 0Ch) reset

value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57

Table 64. TimerValue register bit descriptions . . . . . . . . 57

Table 65. CRCResultLSB register (address: 0Dh) reset

value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57

Table 66. CRCResultLSB register bit descriptions . . . . . 57

Table 67. CRCResultMSB register (address: 0Eh) reset

value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57

Table 68. CRCResultMSB register bit descriptions . . . . 57

Table 69. BitFraming register (address: 0Fh) reset value:

0000 0000b, 00h bit allocation . . . . . . . . . . . . 58

Table 70. BitFraming register bit descriptions . . . . . . . . . 58

Table 71. TxControl register (address: 11h) reset value:

0101 1000b, 58h bit allocation . . . . . . . . . . . . 59

Table 72. TxControl register bit descriptions . . . . . . . . . 59

Table 73. CwConductance register (address: 12h) reset

value: 0011 1111b, 3Fh bit allocation . . . . . . . 60

Table 74. CwConductance register bit descriptions . . . . 60

Table 75. ModConductance register (address: 13h) reset

value: 0011 1111b, 3Fh bit allocation . . . . . . . 60

Table 76. ModConductance register bit descriptions . . . 60

Table 77. CoderControl register (address: 14h) reset value:

0001 1001b, 19h bit allocation . . . . . . . . . . . . 61

Table 78. CoderControl register bit descriptions . . . . . . . 61

Table 79. ModWidth register (address: 15h) reset value:

0001 0011b, 13h bit allocation . . . . . . . . . . . . 62

Table 80. ModWidth register bit descriptions . . . . . . . . . 62

Table 81. ModWidthSOF register (address: 16h) reset

CLRC632

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.7 — 27 February 2014

073937

© NXP Semiconductors N.V. 2014. All rights reserved.

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