AT91SAM9G46 데이터 시트보기 (PDF) - Atmel Corporation

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AT91SAM9G46

AT91 ARM Thumb-based Microcontrollers

Atmel Corporation 

7.3.2.1

7.3.2.2

7.3.2.3

– Static Memory Controller on NCS3, Optional NAND Flash support

– Static Memory Controller on NCS4 - NCS5, Optional CompactFlashM support

Static Memory Controller

• 8-, 16- or 32-bit Data Bus

• Multiple Access Modes supported

– Byte Write or Byte Select Lines

– Asynchronous read in Page Mode supported (4- up to 32-byte page size)

• Multiple device adaptability

– Control signals programmable setup, pulse and hold time for each Memory Bank

• Multiple Wait State Management

– Programmable Wait State Generation

– External Wait Request

– Programmable Data Float Time

• Slow Clock mode supported

DDR2/SDR Controller

• Supports DDR2/LPDDR2, SDR-SDRAM and LPSDR

• Numerous Configurations Supported

– 2K, 4K, 8K, 16K Row Address Memory Parts

– SDRAM with Four Internal Banks

– SDR-SDRAM with 16- or 32- bit Data Path

– DDR2/LPDDR with 16- bit Data Path

– One Chip Select for SDRAM Device (256 Mbyte Address Space)

• Programming Facilities

– Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces

Average Latency of Transactions)

– Timing Parameters Specified by Software

– Automatic Refresh Operation, Refresh Rate is Programmable

– Automatic Update of DS, TCR and PASR Parameters (LPSDR)

• Energy-saving Capabilities

– Self-refresh, Power-down and Deep Power Modes Supported

• SDRAM Power-up Initialization by Software

• CAS Latency of 2, 3 Supported

• Auto Precharge Command Not Used

• SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported

– Clock Frequency Change in Precharge Power-down Mode Not Supported

NAND Flash Error Corrected Code Controller

• Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select

• Single bit error correction and 2-bit Random detection.

• Automatic Hamming Code Calculation while writing

28 AT91SAM9G46

11028BS–ATARM–26-Apr-10

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