ADSP-21371KSWZ-2A2 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21371KSWZ-2A2

SHARC Processor

Analog Devices 

PACKAGE INFORMATION

The information presented in Figure 3 provides details about

the package branding for the ADSP-21371/ADSP-21375 proces-

sor. For a complete listing of product availability, see Ordering

Guide on Page 52.

a

ADSP-2137x

tppZ-cc

vvvvvv.x n.n

yyww country_of_origin

S

Figure 3. Typical Package Brand

Table 10. Package Brand Information

Brand Key

t

pp

Z

ccc

vvvvvv.x

n.n

yyww

Field Description

Temperature Range

Package Type

RoHS Compliant Part

See Ordering Guide

Assembly Lot Code

Silicon Revision

Date Code

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note “Estimating Power Dissipation

for ADSP-2137x SHARC Processors” (EE-318) for detailed

thermal and power information regarding maximum power dis-

sipation. For information on package thermal specifications, see

Thermal Characteristics on Page 46.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 11 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 11. Absolute Maximum Ratings

Parameter

Internal (Core) Supply Voltage (VDDINT)

External (I/O) Supply Voltage (VDDEXT)

Input Voltage –0.5 V to VDDEXT

Output Voltage Swing –0.5 V to VDDEXT

Rating

–0.3 V to +1.5 V

–0.3 V to +4.6 V

+0.5 V

+0.5 V

ADSP-21371/ADSP-21375

Table 11. Absolute Maximum Ratings (Continued)

Parameter

Load Capacitance

Storage Temperature Range

Junction Temperature under Bias

Rating

200 pF

–65°C to +150°C

125°C

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 37 on Page 45 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 4). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Rev. C | Page 17 of 52 | September 2009

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