ADV7403BSTZ-110 데이터 시트보기 (PDF) - Analog Devices
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ADV7403BSTZ-110
Analog Devices
ADV7403BSTZ-110 Datasheet PDF : 20 Pages
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ADV7403
Data Sheet
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). Guaranteed by
characterization.
Table 3.
Parameter
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range1
I2C PORT2
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)3
Data Output Transition Time SDR (CP)4
Data Output Transition Time DDR (CP)4, 5
DATA and CONTROL INPUTS2
Input Setup Time (Digital Input Port)
Input Hold Time (Digital Input Port)
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9:t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
Test Conditions/Comments
Negative clock edge to start
of valid data
End of valid data to negative
clock edge
End of valid data to negative
clock edge
Negative clock edge to start
of valid data
Positive clock edge to end of
valid data
Positive clock edge to start of
valid data
Negative clock edge to end
of valid data
Negative clock edge to start
of valid data
HS_IN, VS_IN
DE_IN, data inputs
HS_IN, VS_IN
DE_IN, data inputs
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
5
45:55
−4 + TLLC1/4
0.25 + TLLC1/4
−2.95 + TLLC1/4
−0.5 + TLLC1/4
9
2.2
7
2
Typ
28.63636
0.6
Max
±50
110
140
400
300
300
55:45
3.6
2.4
2.8
0.1
Unit
MHz
ppm
kHz
MHz
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ms
% duty cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110.
2 TTL input values are 0 V to 3 V with rise/fall times ≥ 3 ns measured between the 10% and 90% points.
3 SDP timing figures obtained using default drive strength value (0xD5) in Subaddress 0xF4.
4 CP timing figures obtained using maximum drive strength value (0xFF) in Subaddress 0xF4.
5 DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
Rev. B | Page 6 of 20
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