LC72133M(1999) 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC72133M
(Rev.:1999)

PLL Frequency Synthesizer for Electronic Tuning

SANYO -> Panasonic 

LC72133M, 72133V

Unlock Detection Timing

1. Unlock Detection Determination Timing

Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle,

unlock determination requires a time longer than the period of the reference frequency. However, immediately after

changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the

reference frequency.

CE

DATA

LATCH

VCO/N

N-

counter

fref

Old data

New data

Old divisor N

New divisor N'

øERROR

(unlock)

The divisor N is not updated

in the first period.

Note: After changing the divisor, øERROR

is output after two fref periods.

Figure 1 Unlocked State Detection Timing

A11936

For example, if fref is 1 kHz, i.e., the period is 1 ms, after changing the divisor N, the system must wait at least 2 ms

before checking for the unlocked state.

VCO

Unlock

detection circuit

÷R

fref

Phase comparator

VCO/N

÷N

DATA LATCH

Preset

UNLOCK

øERROR

L. P. F

A11937

Figure 2 Circuit Structure

No. 5427-18/23

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