CY8C27443(2006) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY8C27443
(Rev.:2006)

PSoC® Mixed-Signal Array

Cypress Semiconductor 

CY8C27x43 Final Data Sheet

Register Map Bank 0 Table: User Space

2. Register Reference

PRT0DR

00 RW

40

ASC10CR0 80 RW

C0

PRT0IE

01 RW

41

ASC10CR1 81 RW

C1

PRT0GS

02 RW

42

ASC10CR2 82 RW

C2

PRT0DM2 03 RW

43

ASC10CR3 83 RW

C3

PRT1DR

04 RW

44

ASD11CR0 84 RW

C4

PRT1IE

05 RW

45

ASD11CR1 85 RW

C5

PRT1GS

06 RW

46

ASD11CR2 86 RW

C6

PRT1DM2 07 RW

47

ASD11CR3 87 RW

C7

PRT2DR

08 RW

48

ASC12CR0 88 RW

C8

PRT2IE

09 RW

49

ASC12CR1 89 RW

C9

PRT2GS

0A RW

4A

ASC12CR2 8A RW

CA

PRT2DM2 0B RW

4B

ASC12CR3 8B RW

CB

PRT3DR

0C RW

4C

ASD13CR0 8C RW

CC

PRT3IE

0D RW

4D

ASD13CR1 8D RW

CD

PRT3GS

0E RW

4E

ASD13CR2 8E RW

CE

PRT3DM2 0F RW

4F

ASD13CR3 8F RW

CF

PRT4DR

10 RW

50

ASD20CR0 90 RW

D0

PRT4IE

11 RW

51

ASD20CR1 91 RW

D1

PRT4GS

12 RW

52

ASD20CR2 92 RW

D2

PRT4DM2 13 RW

53

ASD20CR3 93 RW

D3

PRT5DR

14 RW

54

ASC21CR0 94 RW

D4

PRT5IE

15 RW

55

ASC21CR1 95 RW

D5

PRT5GS

16 RW

56

ASC21CR2 96 RW I2C_CFG

D6 RW

PRT5DM2 17 RW

57

ASC21CR3 97 RW I2C_SCR

D7 #

18

58

ASD22CR0 98 RW I2C_DR

D8 RW

19

59

ASD22CR1 99 RW I2C_MSCR D9 #

1A

5A

ASD22CR2 9A RW INT_CLR0 DA RW

1B

5B

ASD22CR3 9B RW INT_CLR1 DB RW

1C

5C

ASC23CR0 9C RW

DC

1D

5D

ASC23CR1 9D RW INT_CLR3 DD RW

1E

5E

ASC23CR2 9E RW INT_MSK3 DE RW

1F

5F

ASC23CR3 9F RW

DF

DBB00DR0 20 #

AMX_IN

60 RW

A0

INT_MSK0 E0 RW

DBB00DR1 21 W

61

A1

INT_MSK1 E1 RW

DBB00DR2 22 RW

62

A2

INT_VC

E2 RC

DBB00CR0 23 #

ARF_CR

63 RW

A3

RES_WDT E3 W

DBB01DR0 24 #

CMP_CR0 64 #

A4

DEC_DH

E4 RC

DBB01DR1 25 W ASY_CR

65 #

A5

DEC_DL

E5 RC

DBB01DR2 26 RW CMP_CR1 66 RW

A6

DEC_CR0 E6 RW

DBB01CR0 27 #

67

A7

DEC_CR1 E7 RW

DCB02DR0 28 #

68

A8

MUL_X

E8 W

DCB02DR1 29 W

69

A9

MUL_Y

E9 W

DCB02DR2 2A RW

6A

AA

MUL_DH

EA R

DCB02CR0 2B #

6B

AB

MUL_DL

EB R

DCB03DR0 2C #

6C

AC

ACC_DR1 EC RW

DCB03DR1 2D W

6D

AD

ACC_DR0 ED RW

DCB03DR2 2E RW

6E

AE

ACC_DR3 EE RW

DCB03CR0 2F #

6F

AF

ACC_DR2 EF RW

DBB10DR0 30 #

ACB00CR3 70 RW RDI0RI

B0 RW

F0

DBB10DR1 31 W ACB00CR0 71 RW RDI0SYN

B1 RW

F1

DBB10DR2 32 RW ACB00CR1 72 RW RDI0IS

B2 RW

F2

DBB10CR0 33 #

ACB00CR2 73 RW RDI0LT0

B3 RW

F3

DBB11DR0 34 #

ACB01CR3 74 RW RDI0LT1

B4 RW

F4

DBB11DR1 35 W ACB01CR0 75 RW RDI0RO0

B5 RW

F5

DBB11DR2 36 RW ACB01CR1 76 RW RDI0RO1

B6 RW

F6

DBB11CR0 37 #

ACB01CR2 77 RW

B7

CPU_F

F7 RL

DCB12DR0 38 #

ACB02CR3 78 RW RDI1RI

B8 RW

F8

DCB12DR1 39 W ACB02CR0 79 RW RDI1SYN

B9 RW

F9

DCB12DR2 3A RW ACB02CR1 7A RW RDI1IS

BA RW

FA

DCB12CR0 3B #

ACB02CR2 7B RW RDI1LT0

BB RW

FB

DCB13DR0 3C #

ACB03CR3 7C RW RDI1LT1

BC RW

FC

DCB13DR1 3D W ACB03CR0 7D RW RDI1RO0

BD RW

FD

DCB13DR2 3E RW ACB03CR1 7E RW RDI1RO1

BE RW CPU_SCR1 FE #

DCB13CR0 3F #

ACB03CR2 7F RW

BF

CPU_SCR0 FF #

Blank fields are Reserved and should not be accessed. # Access is bit specific.

October 26, 2006

Document No. 38-12012 Rev. *K

17

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