CY7C1442AV33(2005) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1442AV33 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Switching Characteristics Over the Operating Range (continued)[25, 26]
Parameter
tCHZ
tOEV
tOELZ
tOEHZ
Set-up Times
Description
Clock to High-Z[22, 23, 24]
OE LOW to Output Valid
OE LOW to Output Low-Z[22, 23, 24]
OE HIGH to Output High-Z[22, 23, 24]
tAS
tADS
tADVS
tWES
tDS
tCES
Hold Times
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BWX Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up Before CLK Rise
tAH
Address Hold After CLK Rise
tADH
ADSP, ADSC Hold After CLK Rise
tADVH
ADV Hold After CLK Rise
tWEH
GW, BWE, BWX Hold After CLK Rise
tDH
Data Input Hold After CLK Rise
tCEH
Chip Enable Hold After CLK Rise
Shaded areas contain advance information.
250 MHz
Min. Max
2.6
2.6
0
2.6
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
200 MHz
Min. Max.
3.0
3.0
0
3.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
167 MHz
Min. Max
3.4
3.4
0
3.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05383 Rev. *B
Page 20 of 27
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