ADSP-21160M(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21160M
(Rev.:Rev0)

SHARC® DSP Microcomputer

Analog Devices 

ADSP-21160M

JTAG Test Access Port and Emulation

Table 28. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements:

tTCK

TCK Period

tCK

ns

tSTAP

TDI, TMS Setup Before TCK High

5

ns

tHTAP

TDI, TMS Hold After TCK High

6

ns

tSSYS

System Inputs Setup Before TCK Low1

7

ns

tHSYS

System Inputs Hold After TCK Low1

18

ns

tTRSTW

TRST Pulsewidth

4 tCK

ns

Switching Characteristics:

tDTDO

tDSYS

TDO Delay from TCK Low

System Outputs Delay After TCK Low2

13

ns

30

ns

1System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0,

PA, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN,

RESET.

2System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF,

FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS.

7&.

706

7',

7'2

6 < 6 7 (0

,13876

6 < 6 7 (0

2873876

W7&.

W6 7$3

W'7'2

W'6 <6

W+7$3

W66< 6

W+6<6

Figure 28. IEEE 11499.1 JTAG Test Access Port

REV. 0

–41–

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