ADM1064ASU-REEL 데이터 시트보기 (PDF) - Analog Devices

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ADM1064ASU-REEL

Super Sequencer™ with Voltage Readback ADC

Analog Devices 

ADM1064

The device also has several identification registers (read-only),

which can be read across the SMBus. Table 9 lists these registers

with their values and functions.

Table 9. Identification Register Values and Functions

Name

Address Value Function

MANID 0xF4

0x41 Manufacturer ID for Analog

Devices

REVID

0xF5

0x00 Silicon revision

MARK1 0xF6

0x00 S/w brand

MARK2 0xF7

0x00 S/w brand

General SMBus Timing

Figure 31, Figure 32, and Figure 33 are timing diagrams for

general read and write operations using the SMBus. The SMBus

specification defines specific conditions for different types of

read and write operations, which are discussed in the Write

Operations and Read Operations sections.

The general SMBus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data-line SDA, while the serial clock-line SCL remains

high. This indicates that a data stream follows. All slave

peripherals connected to the serial bus respond to the start

condition and shift in the next 8 bits, consisting of a 7-bit

slave address (MSB first) plus a R/W bit. This bit deter-

mines the direction of the data transfer, that is, whether

data is written to or read from the slave device (0 = write,

1 = read).

The peripheral whose address corresponds to the transmit-

ted address responds by pulling the data line low during

the low period before the ninth clock pulse, known as the

acknowledge bit, and holding it low during the high period

of this clock pulse.

1

SCL

91

All other devices on the bus remain idle while the selected

device waits for data to be read from or written to it. If the

R/W bit is a 0, the master writes to the slave device. If the

R/W bit is a 1, the master reads from the slave device.

2. Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an acknowledge bit

from the slave device. Data transitions on the data line

must occur during the low period of the clock signal and

remain stable during the high period, because a low-to-

high transition when the clock is high might be interpreted

as a stop signal. If the operation is a write operation, the

first data byte after the slave address is a command byte.

This tells the slave device what to expect next. It might be

an instruction telling the slave device to expect a block

write, or it might simply be a register address that tells the

slave where subsequent data is to be written. Because data

can flow in only one direction, as defined by the R/W bit,

sending a command to a slave device during a read

operation is not possible. Before a read operation, it might

be necessary to perform a write operation to tell the slave

what sort of read operation to expect and/or the address

from which data is to be read.

3. When all data bytes have been read or written, stop condi-

tions are established. In write mode, the master pulls the

data line high during the 10th clock pulse to assert a stop

condition. In read mode, the master device releases the

SDA line during the low period before the ninth clock

pulse, but the slave device does not pull it low. This is

known as no acknowledge. The master then takes the data

line low during the low period before the tenth clock pulse,

then high during the tenth clock pulse to assert a stop

condition.

9

SDA

0 1 1 0 1 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

START BY

MASTER

ACK. BY

SLAVE

ACK. BY

SLAVE

FRAME 1

SLAVE ADDRESS

FRAME 2

COMMAND CODE

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ACK. BY

SLAVE

D7 D6 D5 D4 D3 D2 D1 D0

FRAME N

DATA BYTE

ACK. BY STOP

SLAVE

BY

MASTER

Figure 31. General SMBus Write Timing Diagram

Rev. 0 | Page 24 of 32

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