AD7653ACPZ 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD7653ACPZ Datasheet PDF : 26 Pages
| |||
AD7653
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND 1
AVDD 2
NC 3
BYTESWAP 4
OB/2C 5
WARP 6
IMPULSE 7
SER/PAR 8
D0 9
D1 10
D2/DIVSCLK0 11
D3/DIVSCLK1 12
AD7653
TOP VIEW
(Not to Scale)
36 AGND
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 DGND
29 BUSY
28 D15
27 D14
26 D13
25 D12
Data Sheet
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE LFCSP PACKAGE HAS AN EXPOSED PAD. THIS EPAD CAN
BE CONNECTED AGND. THIS CONNECTION IS NOT REQUIRED
TO MEET ELECTRICAL PERFORMANCE SPECIFICATIONS.
02966-0-002
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48-1)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1
0
EPAD
1, 36, AGND
P
41, 42
2, 44
AVDD
P
3, 40
NC
4
BYTESWAP DI
5
OB/2C
DI
6
WARP
DI
7
8
9, 10
11, 12
IMPULSE
DI
SER/PAR
DI
D[0:1]
DO
D[2:3]or
DI/O
DIVSCLK[0:1]
Description
Exposed Pad. The LFCSP package has an exposed pad. This EPAD can be connected to AGND. This
connection is not required to meet electrical performance specifications.
Analog Power Ground Pin.
Input Analog Power Pin. Nominally 5 V.
No Connect.
Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift
register.
Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest
mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in
order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power
mode. In this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),
these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that
clocks the data output. In other serial modes, these pins are not used.
Rev. C | Page 8 of 26
Share Link: 