AD7175-8 데이터 시트보기 (PDF) - Analog Devices
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AD7175-8
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AD7175-8 Datasheet PDF : 64 Pages
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Data Sheet
AD7175-8
FILTER CONFIGURATION REGISTER 0
Address: 0x28, Reset: 0x0500, Name: FILTCON0
The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 37. Bit Descriptions for FILTCON0
Bits Bit Name
Settings Description
15
SINC3_MAP0
[14:12] RESERVED
If this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the sinc3 filter for Setup 0. All other
options are eliminated. This allows fine tuning of the output data rate and
filter notch for rejection of specific frequencies. The data rate when on a
single channel equals fMOD/(32 × FILTCON0[14:0]).
These bits are reserved; set these bits to 0.
11
ENHFILTEN0
This bit enables various postfilters for enhanced 50 Hz/60 Hz rejection for
Setup 0. The ORDER0 bits must be set to 00 to select the sinc5 + sinc1
filter for this to work.
0 Disabled
1 Enabled
[10:8] ENHFILT0
These bits select between various postfilters for enhanced 50 Hz/60 Hz
rejection for Setup 0.
010 27 SPS, 47 dB rejection, 36.7 ms settling
011 25 SPS, 62 dB rejection, 40 ms settling
101 20 SPS, 86 dB rejection, 50 ms settling
110 16.67 SPS, 92 dB rejection, 60 ms settling
7
RESERVED
This bit is reserved; set this bit to 0.
[6:5] ORDER0
These bits control the order of the digital filter that processes the
modulator data for Setup 0.
00 Sinc5 + sinc1 (default)
11 Sinc3
[4:0] ODR0
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 0. Rates shown are for the sinc5 + sinc 1
filter. See Table 19 to Table 22.
00000 250,000
00001 125,000
00010 62,500
00011 50,000
00100 31,250
00101 25,000
00110 15,625
00111 10,000
01000 5000
01001 2500
01010 1000
01011 500
01100 397.5
01101 200
01110 100
01111 59.92
10000 49.96
10001 20
10010 16.66
10011 10
10100 5
Reset
0x0
0x0
0x0
0x5
0x0
0x0
0x0
Access
RW
R
RW
RW
R
RW
RW
Rev. 0 | Page 61 of 64
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