AD7175-8 데이터 시트보기 (PDF) - Analog Devices

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AD7175-8

24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers

Analog Devices 

Data Sheet

AD7175-8

SETUP CONFIGURATION REGISTER 0

Address: 0x20, Reset: 0x1320, Name: SETUPCON0

The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.

Table 35. Bit Descriptions for SETUPCON0

Bits Bit Name

Settings Description

[15:13] RESERVED

These bits are reserved; set these bits to 0.

12

BI_UNIPOLAR0

This bit sets the output coding of the ADC for Setup 0.

0 Unipolar coded output

1 Bipolar coded output (offset binary)

11

REFBUF0+

This bit enables or disables the REF+ input buffer.

0 REF+ buffer disabled

1 REF+ buffer enabled

10

REFBUF0−

This bit enables or disables the REF− input buffer.

0 REF− buffer disabled

1 REF− buffer enabled

9

AINBUF0+

This bit enables or disables the AIN+ input buffer.

0 AIN+ buffer disabled

1 AIN+ buffer enabled

8

AINBUF0−

This bit enables or disables the AIN− input buffer.

0 AIN− buffer disabled

1 AIN− buffer enabled

7

BURNOUT_EN0

This bit enables a 10 µA current source on the positive analog input

selected and a 10 µA current sink on the negative analog input selected.

The burnout currents are useful in diagnosis of an open wire, whereby the

ADC result goes to full scale. Enabling the burnout currents during

measurement results in an offset voltage on the ADC. This means the

strategy for diagnosing an open wire operates best by turning on the

burnout currents at intervals, before or after precision measurements.

6

RESERVED

These bits are reserved; set these bits to 0.

[5:4] REF_SEL0

These bits allow the user to select the reference source for ADC

conversion on Setup 0.

00 External reference.

01 External Reference 2 supplied to AIN1/REF2+ and AIN0/REF2− pins.

10 Internal 2.5 V reference. This must also be enabled in the ADC mode register.

11 AVDD1 − AVSS. This can be used to as a diagnostic to validate other

reference values.

[3:0] RESERVED

These bits are reserved; set these bits to 0.

Reset

0x0

0x1

0x0

0x0

0x1

0x1

0x00

0x00

0x2

0x0

Access

R

RW

RW

RW

RW

RW

R

R

RW

R

Rev. 0 | Page 59 of 64

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