ADP3088ARM-REEL 데이터 시트보기 (PDF) - Analog Devices
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ADP3088ARM-REEL Datasheet PDF : 16 Pages
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ADP3088
1. The dc loop gain is limited by the applied load resistance and where VOUT is the nominal dc level. This equation together with
the output resistance of the error amplifier, but it is not important the preceding recommendations should suffice to determine
to determine how high the dc gain is.
compensation component selection for users familiar with loop
2. Two poles in the low frequency spectrum begin to roll off the
gain, one determined by the load resistance and output
capacitor, CO, and the other by the error amplifier’s output
resistance and its termination capacitance, the equivalent
feedback capacitance, and the added compensation capaci-
design. This begins with deciding the crossover frequency, fC,
evaluating the impedances at that frequency, and setting the open-
loop gain, AOL, to unity. By example, fC = 125 kHz is chosen.
Assuming a well chosen CHF as described previously, in other
words, such that it creates a pole well above crossover or approxi-
tance CHF. Determining the location of these poles is not
relevant to the compensation design. It suffices to know that
mately matches the zero of the output capacitor, the following
equation approximates the calculation of the crossover frequency:
both are decades below the crossover frequency.
3. A lead network is especially desirable for a variable output
voltage application in order to keep a fairly constant crossover
frequency and phase margin for all output voltages. If used,
this lead network simply consists of a capacitor, CFF, in parallel
with the upper feedback divider resistor, RA; this creates a
closely spaced zero/pole pair that provides a gain boost before
crossover so that, above the pole frequency, the loop gain and
E phase are similar for all output voltages. If the lead network is
used for a fixed voltage application, the pole should be chosen
to align with the following described zero; for variable voltage
applications, the maximum frequency of the pole should be
T placed as high as is comfortable without substantially degrad-
ing the phase margin, e.g., not within an octave or, more
conservatively, a half-decade of the crossover frequency.
E 4. A zero turns the gain roll-off back to one-pole sufficiently in
advance of the crossover frequency to create ample phase
margin, e.g., half a decade; the zero could feasibly be that of
the output capacitor itself, i.e., the zero formed by the ESR
L and the capacitance, CO, but that is both unlikely (since the
zero frequency will likely be higher than where the loop zero is
desired) and generally imprudent (since the loop performance
would depend on the stability of the ESR, which often is
O poor or unknown). As recommended, the zero, fZ, is created
by an RC circuit terminating the COMP pin (a resistor, RC, in
series with a capacitor, CC), while the capacitance terminating
the error amplifier, CHF, forms a pole, fP, with RC to cancel
S the zero of the output capacitor. Or, if the zero is well above
the crossover frequency, as may be the case when using an
MLC output capacitor, that pole is set high enough above
the crossover frequency, again, for example, half a decade,
B so that it doesn’t cut substantially into the phase margin at
crossover but still ensures continued gain roll-off so that the gain
margin is acceptably high; note that the previous guidelines
suggest that CC ≥ 10 ¥ CHF.
O 5. The gain crosses 0 dB (unity) at a crossover frequency that is
1+
fC =
50k(WA) ¥ fZ ¥ k1
21k(WA) ¥ k1
(16)
where k1 = CO ¥ VOUT/RC and fZ = 1/2p RCCC, the zero frequency
set by the compensation, and the units are shown with the
constants in the equation for clarification.
The preceding equation cannot readily be solved in terms of k1,
but it can be solved closely enough by a few iterations beginning
with values for k1 around 1 ¥ 109 (FA). For the example below, set
the zero about a half-decade below fC as previously advised, that is,
choose fZ ~ fC /÷10 = 40 kHz. Using the previously stated values for
fZ and fC, the value of k1 = 800 p (FA) satisfies the equation. RA
and RB are presumed to be already chosen per earlier guidelines to
set the output voltage. As an example, RA = RB = 10 kW (implying
an output voltage of 2.5 V). Similarly, it is presumed that CO was
chosen; let CO = 15 mF. Then, finally, RC and then also CC can be
determined by rearranging the simple formulas previously given.
The example yields RC ~ 47 kW and CC ~ 82 pF. Assuming an
MLC output capacitor of reasonable quality, the pole setting
capacitor could be chosen to be CHF = 4.7 pF.
VIN
5V
1F
MLCC
CHF
4.7pF
ADP3088
IN
SW
IN
DRV
GND GND
COMP FB
CC
470pF
RC
10k⍀
6.8H
1A
10F
SCHOTTKY MLCC
VOUT
1.5V
RA
10k⍀
RB
48.7k⍀
Figure 2. 5 V to 1.5 V, General-Purpose Application
Another application circuit features a voltage inversion and
regulation design such that the output voltage is negative (see
Figure 3). Negative output voltages are allowed when the input
plus the output voltage does not exceed the rating of the device.
typically a tenth and advisably not greater than a fourth of the
switching frequency; one primary reason for this approximate
upper limit being the extra phase margin loss due to the
In the voltage inverting configuration, the ground reference of
the ADP3088 is the negative output voltage, and the conventional
output voltage point is tied to ground. Operation is bootstrapped;
switching interval that is not predicted by the linear model.
the power converter behaves as if the input voltage were equal to
Assuming no lead network is used, the open-loop gain is given by
ÊV ˆ
AOL
ª
600mËÁ W2 ¯˜ ¥ ZCOMP
VOUT
¥
ZO
(15)
the actual input voltage plus the magnitude of the output voltage
and as if the output voltage were not inverted. This implies that
it is possible to have the input voltage be less than the magnitude
of the output voltage, provided that the input voltage alone is
sufficient to start the operation of the IC, i.e., before the negative
–12–
REV. C
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