ADP2164 데이터 시트보기 (PDF) - Analog Devices
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ADP2164 Datasheet PDF : 19 Pages
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Data Sheet
ADP2164
SPECIFICATIONS
VIN = PVIN = 3.3 V, EN high, SYNC high, TJ = −40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C.
Table 1.
Parameter
Symbol Test Conditions/Comments
Min
Typ
VIN AND PVIN PINS
VIN Voltage Range
VIN
2.7
PVIN Voltage Range
PVIN
2.7
Quiescent Current
IVIN
No switching
895
Shutdown Current
ISHDN
VIN = PVIN = 6.5 V, EN = GND
9
VIN Undervoltage Lockout Threshold UVLO
VIN rising
2.6
VIN falling
2.4
2.5
OUTPUT CHARACTERISTICS
Specified by the circuit in Figure 42
Load Regulation
IO = 0 A to 4 A
0.05
Line Regulation
IO = 2 A
0.05
FB PIN
FB Regulation Voltage
VFB
TJ = −40°C to +125°C
0.591
0.6
FB Bias Current
IFB
0.01
SW PIN
High-Side On Resistance1
VIN = PVIN = 3.3 V, ISW = 500 mA 35
52
Low-Side On Resistance1
VIN = PVIN = 5 V, ISW = 500 mA
30
43
VIN = PVIN = 3.3 V, ISW = 500 mA 24
32
VIN = PVIN = 5 V, ISW = 500 mA
20
29
SW Peak Current Limit
High-side switch, PVIN = 3.3 V
5
6.2
SW Maximum Duty Cycle
Full frequency
SW Minimum On Time2
Full frequency
100
TRK PIN
TRK Input Voltage Range
0
TRK to FB Offset Voltage
TRK = 0 mV to 500 mV
−15
TRK Input Bias Current
FREQUENCY
Switching Frequency
fS
RT = VIN
1.08
1.2
RT = GND
540
600
RT = 91 kΩ
480
600
Switching Frequency Range
500
RT Pin Input High Voltage
1.2
RT Pin Input Low Voltage
SYNC PIN
Synchronization Range
0.5
Minimum Pulse Width
100
Minimum Off Time
100
Input High Voltage
1.2
Input Low Voltage
PGOOD PIN
Power-Good Range
FB rising threshold
105
110
FB rising hysteresis
2.5
FB falling threshold
85
90
FB falling hysteresis
2.5
Power-Good Deglitch Time
From FB to PGOOD
16
Max
6.5
6.5
1100
12
2.7
0.609
0.1
70
55
40
35
7.4
100
600
+15
100
1.32
660
720
1400
0.45
1.4
0.4
115
95
Power-Good Leakage Current
Power-Good Output Low Voltage
VPGOOD = 5 V
IPGOOD = 1 mA
0.1
1
170
220
Unit
V
V
µA
µA
V
V
%/A
%/V
V
µA
mΩ
mΩ
mΩ
mΩ
A
%
ns
mV
mV
nA
MHz
kHz
kHz
kHz
V
V
MHz
ns
ns
V
V
%
%
%
%
Clock
cycles
µA
mV
Rev. C | Page 3 of 19
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