ISL95871C 데이터 시트보기 (PDF) - Renesas Electronics

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ISL95871C

SMBus Interfaced Battery Charger with Internal FETs

Renesas Electronics 

ISL95871C

point in the charge voltage register by more than 300mV, an

internal comparator pulls VCOMP down and turns off both upper

and lower FETs of the buck as in Figure 20. There is a delay of

approximately 1µs between VOUT exceeding the OVP trip point

and pulling VCOMP, LGATE and UGATE low. After UGATE and

LGATE are turned OFF, inductor current continues to flow through

the body diode of the lower FET and VOUT continues to rise until

inductor current reaches zero.

Data Validity

The data on the SDA line must be stable during the HIGH period

of the SCL, unless generating a START or STOP condition. The

HIGH or LOW state of the data line can only change when the

clock signal on the SCL line is LOW. Refer to Figure 22.

SDA

INDUCTOR CURRENT

VOUT

PHASE

BATTERY CURRENT

SCL

DATA LINE CHANGE

STABLE OF DATA

DATA VALID ALLOWED

FIGURE 22. DATA VALIDITY

START and STOP Conditions

As shown in Figure 23, START condition is a HIGH-to-LOW transition

of the SDA line while SCL is HIGH.

The STOP condition is a LOW-to-HIGH transition on the SDA line

while SCL is HIGH. A STOP condition must be sent before each

START condition.

SDA

FIGURE 20. OVERVOLTAGE PROTECTION IN ISL88731C

The System Management Bus

The System Management Bus (SMBus) is a 2-wire bus that

supports bidirectional communications. The protocol is described

briefly here. More detail is available from www.smbus.org.

General SMBus Architecture

VDDSMB

SMBUS MASTER

INPUT

SCL

CONTROL OUTPUT

CPU

INPUT

SDA

CONTROL OUTPUT

SMBUS SLAVE

INPUT

SCL

OUTPUT CONTROL

INPUT

SDA

OUTPUT CONTROL

STATE

MACHINE,

REGISTERS,

MEMORY,

ETC

SMBUS SLAVE

INPUT

SCL

STATE

OUTPUT CONTROL

MACHINE,

INPUT

SDA

OUTPUT CONTROL

REGISTERS,

MEMORY,

ETC

TO OTHER

SLAVE DEVICES

SCL

S

START

CONDITION

P

STOP

CONDITION

FIGURE 23. START AND STOP WAVEFORMS

Acknowledge

Each address and data transmission uses 9-clock pulses. The ninth

pulse is the acknowledge bit (ACK). After the start condition, the

master sends 7-slave address bits and a R/W bit during the next 8-

clock pulses. During the ninth clock pulse, the device that recognizes

its own address holds the data line low to acknowledge. The

acknowledge bit is also used by both the master and the slave to

acknowledge receipt of register addresses and data (see Figure 24).

SCL

1

2

8

9

SDA

START

MSB

ACKNOWLEDGE

FROM SLAVE

FIGURE 24. ACKNOWLEDGE ON THE I2C BUS

FIGURE 21.

FN6856 Rev 2.00

June 8, 2011

Page 13 of 26

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