ISL9012IRJMZ 데이터 시트보기 (PDF) - Renesas Electronics
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ISL9012IRJMZ Datasheet PDF : 12 Pages
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ISL9012
Pin Description
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
PIN
NAME
VIN
EN1
EN2
CBYP
CPOR
GND
NC
POR
VO2
VO1
TYPE
Analog I/O
Low Voltage Compatible
CMOS Input
Low Voltage Compatible
CMOS Input
Analog I/O
Analog I/O
Ground
NC
Open Drain Output (1mA)
Analog I/O
Analog I/O
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
LDO-1 Enable.
DESCRIPTION
LDO-2 Enable.
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
POR Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR output release after LDO-2
output reaches 94% of its specified voltage level (200ms delay per 0.01µF).
GND is the connection to system ground. Connect to PCB Ground plane.
No Connection.
Open-drain POR Output for LDO-2 (active-low).
LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
Typical Application
VIN (2.3V TO 6.5V)
ON
ENABLE 1
OFF ON
ENABLE 2
OFF
ISL9012
1
VIN
10
VO1
2
EN1
9
VO2
3
EN2
4
CBYP
8
POR
7
NC
5
CPOR
6
GND
C1 C2 C3
C4 C5
R1
VOUT 1
VOUT 2 OK
VOUT2 TOO LOW
VOUT2
RESET
(200ms DELAY, C3 = 0.01µF)
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.01µF X5R CERAMIC CAPACITOR
C3: 0.01µF X5R CERAMIC CAPACITOR
R1: 100k RESISTOR, 5%
FN9220 Rev 4.00
December 10, 2015
Page 8 of 12
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