ISL6420A 데이터 시트보기 (PDF) - Renesas Electronics
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ISL6420A Datasheet PDF : 21 Pages
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ISL6420A
VIN
OSC
DRIVER
PWM
COMPARATOR
LO
VOUT
VOSC
+-
DRIVER PHASE
CO
ZFB
VE/A
+-
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1
R2
ZFB
VOUT
ZIN
C3 R3
COMP
R1
-
FB
+
R4
ISL6420A
REF
VOUT
=
VR
EF
1
+
R-R----14-
FIGURE 17. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
FLC=
------------------1--------------------
2 LO CO
(EQ. 4)
FESR= -2---------------E----S--1---R----------C----O-----
(EQ. 5)
The compensation network consists of the error
amplifier (internal to the ISL6420A) and the
impedance networks ZIN and ZFB. The goal of the
compensation network is to provide a closed loop
transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase
margin is the difference between the closed loop phase
at f0dB and 180°. The following equations relate the
compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 17.
Use the following guidelines for locating the poles and
zeros of the compensation network.
Compensation Break Frequency Equations
FZ1 = 2-------------R---1--2---------C-----1--
(EQ. 6)
FP1
=
--------------------------1----------------------------
2
R
2
C-C----1-1----+-----CC----2-2--
(EQ. 7)
FZ2 = 2----------------R-----1----+-1----R-----3------------C----3--
(EQ. 8)
FP2 = 2-------------R---1--3---------C-----3--
(EQ. 9)
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole
(~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop
Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 18 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator
Gain has a high gain peak due to the high Q factor of
the output filter and is not shown in Figure 18. Using
the previously mentioned guidelines should give a
Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at
FP2 with the capabilities of the error amplifier. The Loop
Gain is constructed on the log-log graph of Figure 18
by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
100
80
60
FZ1FZ2 FP1 FP2
OPEN LOOP
ERROR AMP GAIN
40 20LOG
20 (R2/R1)
20LOG
0
(VIN/VOSC)
-20 MODULATOR
GAIN
-40
-60
10
100
FLC
FESR
1k 10k 100k
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 18. ASYMPTOTIC BODE PLOT OF CONVERTER
GAIN
FN9169 Rev 4.00
December 4, 2009
Page 17 of 21
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