
Figure 18. 1-WIRE WRITE- AND READ-TIME SLOTS
WRITE 0 SLOT
tSLOT
tLOW0
tREC
WRITE 1 SLOT
tLOW1
tSLOT
DQ
15ms
DS2761 SAMPLE WINDOW
MIN
TYP
MAX
15ms
30ms
>1ms
15ms
DS2761 SAMPLE WINDOW
MIN
TYP
MAX
15ms
30ms
DS2761
PACK+
PACK-
READ 0 SLOT
tSLOT
DQ
tREC
READ 1 SLOT
tSLOT
PACK+
PACK–
tRDV
MASTER SAMPLE WINDOW >1ms
tRDV
MASTER SAMPLE WINDOW
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
BOTH BUS MASTER AND
DS2761 ACTIVE LOW
DS2761 ACTIVE LOW
RESISTOR PULLUP
Figure 19. SWAP COMMAND TIMING
tSWL
DQ
CC , DC
tSWOFF
tSWON
CC , DC
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