87004AGILF 데이터 시트보기 (PDF) - Integrated Device Technology

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87004AGILF

1:4, Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator

Integrated Device Technology 

ICS87004I Data Sheet

Table 3B. PLL Bypass Function Table

Inputs

SEL3

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

SEL2

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

SEL1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

SEL0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Outputs

PLL_SEL = 0

PLL Bypass Mode

Q[0:3]

÷8

÷8

÷8

÷16

÷16

÷16

÷32

÷32

÷64

÷128

÷4

÷4

÷8

÷2

÷4

÷2

ICS87004AGI REVISION D JANUARY 4, 2010

4

©2009 Integrated Device Technology, Inc.

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