5211AI01 데이터 시트보기 (PDF) - Integrated Circuit Systems
부품명
상세내역
제조사
5211AI01 Datasheet PDF : 13 Pages
| |||
Integrated
Circuit
Systems, Inc.
ICS85211I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85211I-01. In this
example, the input is driven by an ICS HiPerClockS HSTL driver.
The decoupling capacitors should be physically located near
the power pin. For ICS85211I-01, the unused outputs
need to be terminated.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
R6
ICS
50
HiPerClockS
LVHSTL Driv er
U1
5
6
7
8
GND
nCLK
CLK
VDD
nQ1
Q1
nQ0
4
3
2
1
Q0
VDD=3.3V
ICS85211-01
R5
C1
50
0.1u
Zo = 50 Ohm
Zo = 50 Ohm
R1
50
-
+
R2 LVHSTL Input
50
Unused
R3
R4 Output
50
50 Need To
Be
Terminated
85211AMI-01
FIGURE 2. ICS85211I-01 HSTL BUFFER SCHEMATIC EXAMPLE
www.icst.com/products/hiperclocks.html
6
REV. A NOVEMBER 1, 2005
Share Link: 