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ICS8343AY-01LFT

LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER

Integrated Device Technology 

Integrated

ICS8343-01 Circuit

LOW SKEW, 1-TOS-1y6stLeVmCsM, IOnSc./ LVTTL FANOUT BUFFER

ICS8343-01

LOW SKEW, 1-TO-16

LVCMOS / LVTTL FANOUT BUFFETRSD

TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS,

V = V = V = 3.3V±5%

DD

DD1

DD2

OR 2.5V±5%;

VDD = 3.3V±5%, VDD1 = VDD2 = 2.5V±5%, TA = 0° TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical

OE1, OE2

2

VIH

Input High Voltage

CLK

2

OE1, OE2

-0.3

VIL

Input Low Voltage

CLK

-0.3

IIH

OE1, OE2

Input High Current

CLK

VDD = VIN = 3.465V or 2.625V

VDD = VIN = 3.465V or 2.625V

IIL

Input Low Current

OE1, OE2

CLK

V = 3.465V or 2.625V,

DD

VIN = 0V

VDD = 3.465V or 2.625V,

VIN = 0V

-150

-5

VOH

Output High Voltage; NOTE 1

VDD1 = VDD2 = 3.465V

VDD1 = VDD2 = 2.625V

2.6

1.8

VOL

Output Low Voltage; NOTE 1

VDD1 = VDD2 = 3.465V or 2.625V

IOZL

Output Tristate Current Low

IOZH

Output Tristate Current High

NOTE

1:

Outputs

terminated

with

50Ω

to

V /2.

DDx

See

Parameter

Measurement

Information,

"Output Load Test Circuit Diagrams".

Maximum

VDD + 0.3

VDD + 0.3

0.8

1.3

5

150

Units

V

V

V

V

µA

µA

µA

µA

V

V

0.5

V

5

µA

5

µA

TABLE 5A. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V±5%, TA = 0° TO 70°C

Symbol

fMAX

tpLH

tsk(o)

tsk(pp)

tR / tF

odc

Parameter

Output Frequency

Propagation Delay;

NOTE 1

Output Skew; NOTE 2, 4

Part-to-Part Skew;

NOTE 3, 4

Output Rise/Fall Time

Output Duty Cycle

Test Conditions

IJ 200MHz

Measured on rising edge @VDDx/2

Measured on rising edge @VDDx/2

20% to 80%

IJ 133MHz

Minimum

2.0

0.4

45

Typical

Maximum

200

4.0

250

700

1.5

55

Units

MHz

ns

ps

ps

ns

%

tPW

Output Pulse Width

ƒ> 133MHz

tPERIOD/2 - 0.25 tPERIOD/2 tPERIOD/2 + 0.25 ns

All parameters measured at fMAX unless noted otherwise.

NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load

conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

8343AY-01

www.icst.com/products/hiperclocks.html

4

IDT™ / ICS™ LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER

4

REV. B SEPTEMBER 16, 2004

ICS8343-01

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