CDB5345
4. FPGA REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr Function
01h Code Rev. ID
02h MCLK Source
03h Subclock
Source
04h Reserved
05h Transmitter
SDIN Source
7
6
Rev7
Rev6
x
x
Reserved Reserved
0
0
5
Rev5
x
Reserved
1
4
Rev4
x
Reserved
0
3
Rev3
x
Reserved
0
2
Rev2
x
Reserved
0
Reserved Reserved Reserved Reserved Reserved Reserved
0
0
0
Reserved Reserved Reserved
0
0
0
1
Reserved
0
0
Reserved
0
0
Reserved
0
Reserved Reserved Reserved CS8406 Reserved Reserved
0
0
0
1
0
0
1
Rev1
x
Reserved
0
SUBCLK1
0
Reserved
0
Reserved
0
0
Rev0
x
MCLK
0
SUBCLK0
1
Reserved
0
Reserved
1
10
DS658DB1