HIP6502B 데이터 시트보기 (PDF) - Renesas Electronics
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HIP6502B Datasheet PDF : 14 Pages
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HIP6502B
+12VIN
+5VSB
CHF1
CSS
CBULK1
VOUT1
C12V
12V
SS
C5VSB
5VSB
5VDLSB
5VDL
CIN
Q4
VOUT5
VSEN1
CBULK5
CHF5
Q2
CHF3
VOUT3
CBULK3
3V3DLSB
HIP6502B
3V3DL
DLA
5V
Q3
CBULK4
VCLK
VSEN2
Q6
3V3 GND DRV2
Q5
+5VIN
VOUT2 CHF2
Q1 CBULK2
CHF4
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 9. PRINTED CIRCUIT BOARD ISLANDS
A multi-layer printed circuit board is recommended. Figure 9
shows the connections of most of the components in the
converter. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical component
ground connections through vias placed as close to the
component terminal as possible. Dedicate another solid layer
as a power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors for all outputs should be selected to
allow the output voltage to meet the dynamic regulation
requirements of active state operation (S0, S1). The load
transient for the various microprocessor system’s components
may require high quality capacitors to supply the high slew rate
(di/dt) current demands. Thus, it is recommended that the
output capacitors be selected for transient load regulation,
paying attention to their parasitic components (ESR, ESL).
FN4871 Rev.0.00
May 2000
Also, during the transition between active and sleep states,
there is a short interval of time during which none of the power
pass elements are conducting - during this time the output
capacitors have to supply all the output current. The output
voltage drop during this brief period of time can be easily
approximated with the following formula:
V O U T
=
IOUT
E
S
ROUT
+
C-----O--t--t-U----T-
, where
VOUT - output voltage drop
ESROUT - output capacitor bank ESR
IOUT - output current during transition
COUT - output capacitor bank capacitance
tt - active-to-sleep or sleep-to-active transition time (10s typ.)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank, the
choice of capacitors should be such as to maintain the output
voltage above the lowest allowable regulation level.
VCLK (VOUT4) Output Capacitors Selection
The output capacitor for the VCLK linear regulator provides
loop stability. Figure 10 outlines a capacitance vs. equivalent
series resistance envelope. For stable operation and optimized
performance, select a COUT4 capacitor or combination of
capacitors with characteristics within the shown envelope.
10
1
0.1
0.01
10
100
CAPACITANCE (F)
FIGURE 10. COUT4 OUTPUT CAPACITOR
1000
Input Capacitors Selection
The input capacitors for an HIP6502B application have to have
a sufficiently low ESR as to not allow the input voltage to dip
excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the specifications,
certain imbalances between the ATX’s outputs and the
HIP6502B’s regulation levels could have as a result a brisk
transfer of energy from the input capacitors to the supplied
outputs. At the transition between active and sleep states, this
phenomena could result in the 5VSB voltage dropping below
the POR level (typically 4.1V) and temporarily disabling the
Page 11 of 14
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