MAX1002CAX 데이터 시트보기 (PDF) - Maxim Integrated
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MAX1002CAX Datasheet PDF : 12 Pages
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Low-Power, 60Msps, Dual, 6-Bit ADC
AC ELECTRICAL CHARACTERISTICS
(VCC, VCCO = +5V ±5%; TA = +25°C; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (GAIN = open; external 60MHz clock (Figure 7); VINI, VINIQ = 20MHz sine; amplitude -1dB below FS;
unless otherwise noted.)
Maximum Sample Rate
Analog Input -0.5dB Bandwidth
Effective Number of Bits
Signal-to-Noise and Distortion
Ratio
fMAX
BW
ENOBM
ENOBH
ENOBL
SINAD
Gain = GND, open, VCC
GAIN = open (mid gain)
GAIN = open (mid gain),
VIN = 50MHz, -1dB below FS
Gain = VCC (high gain)
Gain = VCC (low gain)
Gain = open (mid gain)
60
55
5.6
5.85
5.7
5.8
5.85
35.4
37
Msps
MHz
Bits
dB
Input Offset (Note 5)
OFF
Crosstalk Between ADCs
XTLK
Offset Mismatch Between ADCs OMM2
I channel
Q channel
(Note 5)
-0.5
0.5
LSB
-0.5
0.5
-55
dB
-0.5 ±0.25 0.5
LSB
Amplitude Match Between
ADCs
AM
-0.2 ±0.1 0.2
dB
Phase Match Between ADCs
PM
TIMING CHARACTERISTICS (data outputs: RL = 1MΩ, CL = 15pF, Figure 8)
DCLK to Data-Propagation
Delay
tPD
(Note 6)
-2
±0.5
2 degrees
7.1
ns
Data Valid Skew
Input to DCLK Delay
Aperture Delay
Pipeline Delay
tSKEW
tDCLK
tAP
PD
(Note 6)
TNK+ to DCLK (Note 6)
3.6
ns
5.3
ns
5.5
ns
1
clock
cycle
Note 1: Best straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4, 5).
Note 3: PSSR is defined as the change in the mid-gain, full-scale range as a function of the variation in VCC supply voltage
(expressed in decibels).
Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply
transients and achieve the best dynamic performance, reduce the capacitive loading effects by keeping line lengths on the
digital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2, 3).
Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. tDCLK is measured from the 50% level of the clock overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
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