MH64D72KLG-10 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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MH64D72KLG-10

4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH64D72KLG-75,-10

4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

AC TIMING REQUIREMENTS(Continues)

(Ta=0 ~ 70 OC , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)

Symbol

AC Characteristics

Parameter

-75

Min. Max.

-10

Min. Max.

Unit Notes

tRAS

Row Active time

45 120,000 50 120,000 ns

tRC

tRFC

tRCD

tRP

tRRD

tWR

tDAL

tWT R

tXSNR

tXSRD

tXPNR

tXPRD

Row Cycle time(operation)

65

Auto Ref. to Active/Auto Ref. command period 75

Row to Column Delay

20

Row Precharge time

20

Act to Act Delay time

15

Write Recovery time

15

Auto Precharge write recovery + precharge time 35

Internal Write to Read Command Delay

1

Exit Self Ref. to non-Read command

75

Exit Self Ref. to -Read command

200

Exit Power down to command

1

Exit Power down to -Read command

1

70

ns

80

ns

20

ns

20

ns

15

ns

15

ns

35

ns

1

tCK

80

ns

200

tCK

1

tCK

1

tCK 18

tREFI Average Periodic Refresh interval

7.8

7.8

us 17

Output Load Condition

(f or component measurement)

VO U

VTT =V REF

10cm

50ohm

Zo=50 ohm

30pF

V REF

DQS

DQ

Output Timing

Measurement

Reference

Point

VREF

VREF

MIT-DS-0389-1.1

MITSUBISHI ELECTRIC

20.Nov.2000

19

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