MH64D72KLG-10 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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MH64D72KLG-10
MITSUBISHI ELECTRIC
MH64D72KLG-10 Datasheet PDF : 38 Pages
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS (Component Level)
(Ta=0 ~ 70 OC , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Sy m bol
AC Characteristics
Parameter
tAC DQ Output Valid data delay time f rom CLK//CLK
-75
Min.
Max.
-0.75 +0.75
-10
Min.
Max.
-0.8
+0.8
Unit Notes
ns
tDQSCK DQ Output Valid data delay time f rom CLK//CLK
-0.75 +0.75
-0.8
+0.8
ns
tCH CLK High lev el width
tCL CLK Low lev el width
tHP CLK half period
0.45
0.55
0.45
0.55 tCK
0.45
0.55
0.45
0.55 tCK
min(tCL,
tCH
min(tCL,t
CH
ns
20
tCK CLK cycle time
CL=2.5
7.5
15
8
15
ns
CL=2
10
15
10
15
ns
tDH Input Setup time (DQ,DM)
0.5
tDS Input Hold time(DQ,DM)
0.5
tDIPW DQ and DM input pulse width (f or each input)
1.75
tHZ Data-out-high impedance time f rom CLK//CLK
-0.75
tLZ Data-out-low impedance time f rom CLK//CLK
-0.75
tDQSQ DQS-DQ Skew(f or DQS and associated DQ signals)
tDQSA DQS-DQ Skew(f or DQS and all DQ signals)
tQH DQ/DQS output hold time f rom DQS
tHP-0.75
tDQSS Write command to f irst DQS latching transition
0.75
tDQSH DQS input High lev el width
0.35
tDQSL DQS input Low lev el width
0.35
tDSS DQS f alling edge to CLK setup time
0.2
tDSH DQS f alling edge hold time f rom CLK
0.2
tMRD Mode Register Set command cycle time
15
tWPRES Write preamble setup time
0
tWPST Write postamble
0.4
tWPRE Write preamble
0.25
tIS Input Setup time (address and control)
0.9
tIH Input Hold time (address and control)
0.9
tRPST Read postamble
0.4
tRPRE Read preamble
0.9
+0.75
+0.75
+0.5
+0.5
1.25
0.6
0.6
1.1
0.6
0.6
2
-0.8
-0.8
tHP-1.0
0.75
0.35
0.35
0.2
0.2
15
0
0.4
0.25
1.2
1.2
0.4
0.9
+0.8
+0.8
+0.6
+0.6
1.25
0.6
0.6
1.1
ns
ns
ns
ns
14
ns
14
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
16
tCK 15
tCK
ns 19
ns 19
tCK
tCK
MIT-DS-0389-1.1
MITSUBISHI ELECTRIC
20.Nov.2000
18
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